Async 2004is the tenth in the series of annual symposia on self-timed and
asynchronous circuit techniques, with special focus on state-of-the-art
and innovative application domains where asynchronous techniques can help
improve performance, power consumption, reliability, low EM radiation,
or design time. Topics of current interest include, but are not necessarily
limited to:
- Mixed synchronous/asynchronous architectures, interfaces and circuits
- Pipelined high-speed & low-power asynchronous logic, memories, and interconnect
- High-level design and synthesis of self-timed circuits
- Physical design of unclocked logic and pipelines
- Formal methods for self-timing and performance analysis
- Test, reliability, security and radiation tolerance
- CAD for asynchronous design and validation
- Globally-Asynchronous Locally-Synchronous systems (GALS)
- Asynchronous System-on-a-Chip (SoC) integration of IP modules
- Novel asynchronous architectures
- Asynchrony and latency tolerance in system-level design
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SUBMISSION INFORMATION |
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Submission Deadline: |
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Notification of Acceptance: |
31st of December 2003. |
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Final Version Due: |
2nd of February 2004. |
Paper submission is now past: Submissions site
is now closed
PAPER FORMAT
- Abstract of up to 150 words.
- 10 Pages or less, including Figures.
- Single spaced, 10pt or larger font size, or IEEE format.
The Conference Proceedings will be published by the IEEE Computer Society Press.
Queries about paper submissions may be sent to the
Program Committee Chairs.
